74G clock buffer
I measured the 1:4 and 1:10 clock buffers and noticed a change in
edge speeds. The 1:4 measured at 256psec and 272psec rise/fall.
(This compares with 204psec rise and 284ps fall for the 1:2 buffer).
The average is slightly slower, but the edges are more symmetrical.
I expected the 1:4 might be slightly slower due to the larger fan
out internal to the buffer than for the 1:2. However, I expected
that since the
1:2 package heavily favors the GND return path, that the fall time
would be much faster than the rise time, contrary to the
measurements.
The 1:10 measured at 272ps rise and 264ps fall, slightly slower
still, but very symmetrical edges.
Thank you,
------/ --/ -----/ -----/IBM@IBMUS
Drive 50 Ohm load
Drive 50 Ohm load
Comments
Thank you for sending me those photos.
More Vdd pins or more gnd pins will change the rise/fall time.
You are absolutely right.
Equal Vdd & gnd pins are the best.
However, we make IC pin configuration exactly the same as the other semiconductor companies. For example, PO74G38072 & PO74G38074 are from IDT IDT74FCT38072 & IDT74FCT38074. Potato PO49FCT3807B is the same as Philips PCK3807A, IDT/ICS MK3807-01, Cypress CY2CC810, Pericom PI49FCT3807D etc.
We are using GHz CMOS technology.
We have much better products but they have much bigger market.
So we are not able to change pin configuration.
For a CMOS output, rise time is depending on PMOS & the pass of Vdd pin.
The fall time is depending on NMOS & the pass of GND pin.
We are not able to change Vdd & GND pin configuration, but we can change the size of PMOS & NMOS.
PO49FCT3807B is the update version. We create B version base on the characterization data of previous 3807. So the rise & fall time are very symmetrical edges.
38072 & 38074 are A version. A version is base on the simulation result.
But simulation result is always not very accurate.
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Posted by: PotatoSemi | March 8, 2008 04:05 AM